Nowadays, when the scale of connectivity is continuously growing, the IoT market is steadily expanding and privacy issues are mainstream, Deep Packet Inspection is more relevant than ever. Law enforcement agencies, media companies, internet service providers or any other organizations that aim to prevent cyberattacks and reveal user data in-depth as a rule deal with Deep packet inspection (DPI). On the other hand, ever-growing high-speed networks are such a challenge for DPI technology and it is far from being able to process the traffic at the line speed.
In this regard, software solutions are proved to be not competent enough and hardware-based acceleration is needed. Grovf offers the GRegex IP - PCRE compatible regular expression algorithm on FPGA chip achieving 100 Gbps throughput with a single IP core.
Today’s traffic and DPI
Deep packet inspection (DPI) is an advanced technique of analyzing and managing network traffic. This next-generation technology is able to inspect every byte of each packet, that is to say, headers, application types and actual packet content. DPI has a wide range of use cases but the majority of them comes out of enterprise network security - combat malware, prevent data leaks, identify and deter hackers, gather intimate details about user behavior, etc.
The growing importance of this sphere, today’s traffic and the high speed of networks put severe pressure on this vital security tool. Telecommunication companies started to deploy 100 Gbps links, the 400 Gbps Ethernet standard has recently been ratified, and large data centers already call for a 1 Tbps technology. Consequently, despite many proposed optimizations, existing DPIs still lack the capacity to process high-speed network traffic at the line speed. Usually, software-based solutions can achieve a 10 Gbps throughput, while the one of 100 Gbps is far beyond their capabilities. To achieve this level of speed, Grovf offers hardware (FPGA) acceleration - processing network traffic at 100 Gbps speeds in single-box DPIs.
Why choose FPGA for DPI acceleration?
- Direct interaction with the network traffic in the chip layer without the need for transferring data to the Operating system (OS) and software layer
- Performant enough as an ASIC for certain workloads
- Flexible enough to reconfigure, change schemas, test the market, proof the solution, adjust development, build a viable product based on customer feedback
Learn more about 100Gbps Network DPI and Content Extraction on Xilinx’s FPGA.
Learn more about GRegex IP - Grovf solution for DPI acceleration.