RDMA

The Grovf RDMA IP core and host drivers provide RDMA over Converged Ethernet (RoCE v2) system implementation and integration with standard Verbs API.
RDMA IP is delivered with reference design which includes the IP subsystem itself the 100G MAC IP subsystem, DMA subsystem, host drivers, and example application on software. The system drivers are integrated with OFED standard Verbs API and are compatible with well-known RNIC cards and software. The system provides low latency FPGA implementation of RoCE v2 at 100 Gbps throughput.

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100 Gbps

Throughput

< 2 us

Latency

Verbs

API

High Performance Computing

As more computer activities migrate to cloud platforms and software systems become more standardized, companies are seeking methods to include HPC into their data operations. To execute HPC, data centers require computers and servers ready to handle large-scale data, as well as a nearly failsafe networking solution between them. The HPC cluster will be performing quadrillions of calculations per second, and the network infrastructure must be able to immediately sequence and analyze data

Storage Clustering and Disaggregation

The performance of local storage is combined with the flexibility of storage area networks in disaggregated storage. Modern storage clusters are moving forward to meet 100Gbps network infrastructure as the demand for data access performance and latency grows. High-performance links between storage nodes are a key component for building a disaggregated storage cluster solution. With this saying, RoCE V2 is a technology that enables data movement between servers providing both flexibility and performance at scale.

Memory Pooling

Memory pooling is a key component when building multi-master node computing servers to perform database operations. Often database systems have to make tradeoffs between data validity, availability, atomicity and read/write performance. This is due to the fact that generally database systems are designed with a single master node and there is no single memory pool that can enable multi-master node architecture.