GROVF Inc. releases low latency RDMA RoCE V2 FPGA IP Core for Smart NICs
GROVF team is extremely excited to announce that have released a low latency RDMA RoCE V2 FPGA IP Core for Smart NICs. This new IP core will democratize the RNIC market and enable FPGA-based smart NIC producers as well as system integrators to develop and deploy RNIC use-cases.
"We've been working on this IP for more than a year and a half now to bring the RNIC enablement to FPGA-based NICs," says Artavazd Khachatryan, CTO at Grovf. "Though the IP is built on FPGA, we have not compromised the latency and throughput compared to industry-leading ASIC based RNIC producers. Coupled with in-line offload and acceleration capability of FPGA, Grovf RDMA RoCE v2 IP will trigger applications such as storage clustering and disaggregation offload, HPC application offload, algorithmic trading, database memory pooling, and more."
Features and benefits of the solution include
- 100Gbps line rate.
- Under 2-microsecond round-trip latency.
- Standard Verbs API support.
- Compatibility to Channel Adapter and RoCE v2 requirements of InfiniBand specification.
- Fully compatible with known RNIC products and soft RoCE implementations.
The RoCE v2 FPGA IP will be available for partners and interested customers starting from Dec. 1, 2021.