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Senior Design Verification Engineer
Yerevan, Armenia

Come join the company leading the technological revolution in data center infrastructure. Grovf is a technology company producing groundbreaking 400Gbps network processors that enables cybersecurity, HPC, and storage use cases.

The ASIC Verification Engineer's primary job function is Pre-Silicon Design Verification of Network processor accelerator IPs and SOC designs using industry-standard verification methodologies.


Job Responsibilities:


  • Pre-Silicon Design verification of next-generation Network processor accelerator IPs and SoCs, blocks, and/or chip top-level.

  • Collaborate with other team members to define a verification methodology and a test plan.

  • Develop IP-level verification environments including stimulus generators, monitors, scoreboards, and coverage collectors

  • Build self-checking test benches for SoC blocks and chip top-level verification.

  • Develop a verification plan for IP and SOC features

  • Generate directed and random test cases, write regression scripts, and report code and functional coverage.

  • Do a first-level debug for root cause classification (TB, HW, or SW issue), and work with the design team to validate fixes or workarounds.

  • Run Gate level simulations, and replicate Silicon/FPGA bugs in the test bench environment.

  • Develop and grow verification infrastructure to improve verification productivity and regression management

  • Contribute to identifying and adopting best engineering practices with cross-functional teams


Required Qualifications:


  • BS/MS in Electrical Engineering or related degree or certification required.
  • 5+ years of experience in System Verilog or UVM bUVM-based verification
  • Good skills in verification methodology, test planning, and test bench architecture
  • Very good experience with System Verilog and advanced verification techniques: constrained random verification, code/functional/assertion coverage.
  • Experience in integrating Verification IPs, and HW/SW Co-Simulation is a plus.
  • Knowledge of RISC-V-based SoC architecture and system busses (AHB, AXI, CHI) is strongly desired.
  • Knowledge of standard SoC interfaces and high-speed IO protocols (PCIe, DDR, Ethernet) is a plus.
  • Programming skills in C++, Python, and shell scripting are desired.