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Mid ASIC RTL Design Engineer
Yerevan, Armenia
We are looking for an RTL design engineer to join our team and work on the next-generation server infrastructure. You will be a part of a team of highly professional engineers working with the world’s leading ASIC design companies to conceptualize and build the new server platform ASIC. Time-to-time you will work with processors and other hardware IPs that are not publicly available yet. Your team will work with all the cutting-edge technologies like CPUs, Memories, Busses (PCIe5, UCIe), cache coherent interconnects, and many more. 
Grovf is a leading company providing the networking technologies IPs for the datacenters and currently is actively working on the next generation server designs.

Required Qualifications:


  • 3 + years of experience in digital design with one or more HDL languages (System Verilog, Verilog, VHDL)

  • 3 + years experience in one or more scripting languages (TCL, Python, Perl)

  • Understanding of Standard Cell ASIC development flow including digital design, IP integration, simulation, and synthesis

  • B.S. or M.S. degree in Computer Engineering, Computer Science, or Electrical Engineering

  • Proficiency in Intel / Altera and/or Xilinx FPGAs is a plus

  • Understanding of computer architecture (CPUs, DMA, PCIe) is a plus


Job Responsibilities:

  • Interact closely with the Architecture team and develop microarchitecture and coding to meet quality and Performance Power Area (PPA) for the IP

  • Perform RTL coding, function/performance simulation debug, and Lint checks.

  • Participate in synthesis, timing/power closure, and silicon bring-up

  • Participate in test plan and coverage analysis of the IP, sub-system, and chip-level verification

  • Work with multi-disciplined and multi-site teams in RTL design, verification, DFT, physical design, software team and architects.